System and method for providing an output signal without or with reduced jitter based upon an input signal notwithstanding phase changes in a clock signal

ABSTRACT

Systems and methods for providing an output signal based at least in part upon an input signal and a clock signal in a manner in which jitter is avoided or diminished, including for example a digital-to-analog converter (DAC), are disclosed herein. In one example embodiment, such a system includes an output signal generating component, a first component having a first switch and a variable characteristic, and a plurality of second components each having a respective additional switch and a respective fixed characteristic. A value of the variable characteristic is set at least in part based upon input and clock signals so that, when the variable characteristic influences at least indirectly the generating of the output signal by the output signal generating component, the output signal attains a first level that at least indirectly depends upon a phase of the clock signal relative to the input signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

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STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

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FIELD OF THE DISCLOSURE

The present disclosure relates to systems and methods for signalprocessing and more particularly, for example, to systems and methodsfor processing signals to reduce or eliminate jitter.

BACKGROUND OF THE DISCLOSURE

Many systems require digital processing even when the input and/oroutput signals are analog signals. This is often the case, for example,in the context of conventional speed or transmission (e.g., enginetransmission) sensing systems. In at least some such conventionalsensing systems, speed is sensed by detecting zero crossings of amagnetic field that occur as magnetic teeth on a wheel rotate past amagnetic sensor (e.g., a Hall sensor, an anisotropic magnetoresistance(AMR) sensor, a tunnel magnetoresistance (TMR) sensor, or a giantmagnetoresistance (GMR) sensor) and induce change(s) in the outputvoltage of the magnetic sensor. In such embodiments, after each zerocrossing, the supply current of the sensor is set to a new level.Additionally, in such embodiments, all calculations on the incomingsignal are performed digitally, so the supply current can only changeafter an edge of the internal clock signal. This limits the accuracy ofthe zero-crossing detection, and the quantization in the time domainadds to the overall jitter of the system.

Referring to FIG. 1, a first graph 100, second graph 102, and thirdgraph 104 collectively illustrate how variations in the timing of aclock signal relative to the timing of an input signal 106 can result insignificantly different output signals and corresponding jitter. Moreparticularly, the first graph 100, second graph 102, and third graph 104respectively illustrate a first clock signal 108, second clock signal110, and third clock signal 112, respectively. Although the first,second, and third clock signals 108, 110, and 112 share in common thesame frequency, the three clock signals are slightly out of phaserelative to one another. Consequently, as shown in the first, second,and third graphs 100, 102, and 104, the first, second, and third clocksignals 108, 110, and 112 respectively have first, second, and thirdvalues 114, 116, and 118, respectively that differ from one another at atime 120 at which the input signal 106 crosses zero occurs. Moreparticularly, the first value 114 of the first clock signal 108 is aminimum value of that clock signal at the time 120, the third value 118of the third clock signal 112 is a maximum value of that clock signal atthe time 120, and the second value 116 of the second clock signal 110 isa transitional (downward edge) value of that clock signal at the time120 that can be considered to be in between (e.g., a zero value) of thesecond clock signal 110.

Because of this variation in the relative timing of the first, second,and third clock signals 108, 110, and 112 relative to one another andrelative to the input signal 106, as further illustrated in FIG. 1virtual phase error is introduced into output signals generated basedupon the interplay of the input signal 106 and the clock signals 108,110, and 112. More particularly, in the first graph 100, it can be seenthat a first output signal 122 is step-shaped and includes a series ofsteps 124 that are each of equal height and width relative to thepreceding step, that a first step 126 of the series of steps 124 occursa first time differential 128 after the time 120, and that the series ofsteps has an effective slope represented by a dashed line 130. Bycomparison, in the second graph 102, it can be seen that a second outputsignal 132 also is step-shaped and includes a series of steps 134 thatare each of equal height and width relative to the preceding step, thata first step 136 of the series of steps 134 occurs a second timedifferential 138 after the time 120, and that the series of steps has aneffective slope represented by a dashed line 140. Additionally bycomparison, in the third graph 104, it can be seen that a third outputsignal 142 also is step-shaped and includes a series of steps 144 thatare each of equal height and width relative to the preceding step, thata first step 146 of the series of steps 144 occurs a third timedifferential 148 after the time 120, and that the series of steps has aneffective slope represented by a dashed line 150.

In view of these considerations, as further illustrated in FIG. 1, thefirst, second, and third output signals 122, 132, and 142 are not inphase within one another even though the three output signals are allgenerated based upon the same input signal, namely, the input signal106. More particularly, it can be seen from the first graph 100 that afirst virtual starting point 152 of the first output signal 122, namely,the point at which the dashed line 130 crosses an initial (e.g., zero)level 154 of the first output signal, occurs a first time amount 156 inadvance of the time 120. By contrast, it can be seen from the secondgraph 102 that a second virtual starting point 162 of the second outputsignal 132, namely, the point at which the dashed line 140 crosses aninitial (e.g., zero) level 164 of the second output signal, occurs asecond time amount 166 in advance of the time 120 that is less than thefirst time amount 156. And further by contrast, it can be seen from thethird graph 104 that a third virtual starting point 172 of the thirdoutput signal 142, namely, the point at which the dashed line 150crosses an initial (e.g., zero) level 174 of the third output signal,occurs a third time amount 176 in advance of the time 120 that is lessthan each of the first time amount 156 and the second time amount 166.Accordingly, because of the differences in the timing of the clocksignals 108, 110, and 112, the output signals 122, 132, and 142 are outof phase relative to one another, and such differences correspond to theproducing of jitter in the overall output signal during operation inwhich a given clock signal varies in its phase over time.

Although efforts have been made to develop modified systems and methodsfor signal processing to alleviate such concerns, such modified systemsand methods have other disadvantages. For example, one manner ofaddressing the above-discussed problems relating to jitter andassociated inaccuracy involves increasing the clock frequency to a levelat which the clock is no longer the dominant jitter source. However,this strategy can result in increased total power consumption andnecessitate higher timing constraints on the digital signal processing,neither of which are desirable.

For at least these reasons, therefore, it would be advantageous if oneor more improved systems and methods for signal processing could bedeveloped that addressed one or more of these concerns or disadvantagesrelating to jitter, and/or one or more other concerns or disadvantages.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows three graphs illustrating in an exemplary manner the phaseerror that can be caused by a sampling clock during the operation ofconventional sensing circuits;

FIG. 2 is a schematic diagram showing an improved speed sensor systemencompassing pulse shaping digital-to-analog converter (DAC) circuitryin accordance with an example embodiment encompassed herein;

FIG. 3 shows three graphs illustrating phase error reduction that isachieved in improved speed sensor systems employing pulse shaping DACcircuitry such as that of FIG. 2;

FIG. 4 is a schematic diagram showing, in a generalized form, acurrent-domain topology of DAC circuitry that can be implemented in thespeed sensor system of FIG. 2;

FIG. 5 is a schematic diagram showing, in a generalized form, avoltage-domain topology of DAC circuitry that can be implemented in thespeed sensor system of FIG. 2;

FIG. 6 is a schematic diagram showing an additional current-domaintopology of DAC circuitry that can be implemented in the speed sensorsystem of FIG. 2; and

FIG. 7 is a schematic diagram showing an additional voltage-domaintopology of DAC circuitry that can be implemented in the speed sensorsystem of FIG. 2.

DETAILED DESCRIPTION

The present disclosure encompasses a variety of embodiments of systemsand methods for signal processing including, for example, systems andmethods for processing speed sensing signals so as to reduce jitter orto avoid or reduce output signal variation notwithstanding phasevariation in a clock signal. For example, such systems and methods allowfor an output signal to be provided based at least indirectly upon aninput signal and a clock signal in a manner so that, notwithstanding oneor more phase changes in the clock signal, the output signalsubstantially or entirely retains a consistent phase relative to theinput signal over a time period corresponding to a plurality of periodsof the clock signal. Also, in at least some embodiments, the signalprocessing system employs, or the signal processing method involves, apulse-shaping digital-to-analog converter (DAC) that is configured toreduce jitter (which otherwise might be caused by limited clockfrequencies), by making use of a limited slope of an output pulse. Byaligning a virtual starting point of the slope with an actualzero-crossing, the jitter can be reduced without increasing the clockfrequency.

Further, in at least some embodiments, the present disclosure concerns asolution that reduces the effect of time quantization by internalclocking without increasing the clock frequency. To minimize emission,pulse shaping on the supply current is applied. Pulse shaping limits theslope of the output pulse. A slope between 8 mA/us and 26 mA/us iscommon for these types of sensors. The pulse shaping can be performed ina fully analog manner or with a DAC, but in both cases the slope beginsafter (or at a time of) an edge of the internal clock (that is, the sameor substantially the same principles described herein as beingapplicable with respect to a DAC can also be utilized in achieving pulseshaping by way of a fully analog solution). In at least someembodiments, the first DAC step is adapted to make the virtual startingpoint of the slope independent of the clock phase, even though other DACsteps remain the same. With this approach the effect of timequantization can be substantially or completely compensated for oreliminated.

Referring to FIG. 2, a schematic diagram is provided to show an improvedspeed sensor system 200 that includes a pulse-shaping digital-to-analogconverter (DAC) 202 in accordance with an example embodiment encompassedby the present disclosure. More particularly shown, the speed sensorsystem 200 includes a sensor array 204 that detects or senses quantitiesor characteristics of a sensed device (for example, the magnetic fieldof a rotating wheel or other rotating component, not shown) and providesone or more output signals as represented by an arrow 206 to one or moresignal processing or conversion components 208. The components 208, uponcompletion of appropriate conversion or processing, in turn outputsignals as represented by an arrow 210 to an analog-to-digital converter(ADC) 212. The ADC 212 converts the signals received from the components208 from analog values into digital values that are output as digitalsignals as represented by an arrow 214.

Further as shown, the digital signals represented by the arrow 214 inturn are provided to offset correction circuitry 216, at which offsetcorrection is performed and offset corrected signals are output asrepresented by an arrow 218. The offset corrected signals in turn areprovided to zero crossing detection circuitry 220, at which a zerocrossing detection operation is performed. Subsequently, zero crossingdetection output signals as represented by an arrow 222 are providedfrom the zero crossing detection circuitry 222 to protocol generatorcircuitry 224. The protocol generator circuitry 224 in turn providesoutput signals represented by an arrow 226 to the pulse-shaping DAC 202.In turn, the pulse-shaping DAC 202 provides output signals, in the formof current signals as represented by an arrow 228, to terminals VDD andGND of the system 200.

The voltage regulator, as shown by an array of arrows 232 is coupled toeach of the sensor array 204, the ADC 212, the offset correctioncircuitry 216, the zero correction detection circuitry 220, the protocolgenerator circuitry 224, and the pulse-shaping DAC 202. Also as shown,the regulator 230 is coupled to the terminal VDD as represented by anarrow 233, to which the pulse-shaping DAC 202 is coupled as discussedabove (and which can also be coupled to, or be considered to constitute,a voltage source). Additionally, each of the regulator 230, sensor array204, components 208, ADC 212, offset correction circuitry 216, zerocrossing detection circuitry 220, protocol generator circuitry 224, and(as already mentioned above) pulse-shaping DAC 202 are all coupled toground (the terminal GND) as well, as indicated by an array of arrows234. In addition to the above-described components, the speed sensorsystem 200 further includes an oscillator 236, a NV memory 238, and anelectro static discharge (ESD) protection circuitry 240. The oscillator236 particularly serves to a provide a clock signal (not shown in FIG.2) to the ADC 212, offset correction circuitry 216, zero crossingdetection circuitry 220, protocol generator circuitry 224, andpulse-shaping DAC 202. Also, in at least some embodiments (and althoughnot shown in FIG. 2), a reconstruction filter is employed after (e.g.,at the output of) the pulse-shaping DAC 202. In such embodiments, such afilter can in some implementations have a bandwidth of approximately 1.5MHz (albeit the bandwidth of the system is not really a limitingfactor). Also, it should be appreciated that the clock on the receiverside will determine the overall performance of the system.

In accordance with the present embodiment of FIG. 2, the sensing system200 having the pulse-shaping DAC 202 provides an output signal (oroutput signals, e.g., as represented by the arrow 228) with reducedclock-induced jitter by comparison with conventional sensing systems.That is, although in conventional systems such as those represented byFIG. 1, variations in the phase or timing of a clock signal asillustrated by the clock signals 108, 110, and 112 can result invariations in an output signal as illustrated by the output signals 122,132, and 142, implementation of a pulse-shaping DAC such as the DAC 202fully or substantially eliminates such output signal variation. Exampleoperation of the pulse-shaping DAC 202 to achieve such reduced-jitter orjitter-free performance is illustrated by FIG. 3.

More particularly, FIG. 3 shows a first graph 300, second graph 302, andthird graph 304 that collectively illustrate how implementation of thepulse-shaping DAC 202 achieves output signals generated based upon aninput signal 306 that are identical or substantially identical in termsof their timing notwithstanding variations in the timing of a clocksignal used to generate those output signals. More particularly, thefirst graph 300, second graph 302, and third graph 304 respectivelyillustrate a first clock signal 308, second clock signal 310, and thirdclock signal 312, respectively, which share in common the same frequencybut are slightly out of phase relative to one another. Consequently, asshown in the first, second, and third graphs 300, 302, and 304, thefirst, second, and third clock signals 308, 310, and 312 respectivelyhave first, second, and third values 314, 316, and 318, respectively,which differ from one another at a time 320 at which the input signal306 crosses zero. More particularly, the first value 314 of the firstclock signal 308 is a minimum value of that clock signal at the time320, the third value 318 of the third clock signal 312 is a maximumvalue of that clock signal at the time 320, and the second value 316 ofthe second clock signal 310 is a transitional (downward edge) value ofthat clock signal at the time 320 that can be considered to be inbetween (e.g., a zero value) of the second clock signal 310.

Notwithstanding this variation in the relative timing of the first,second, and third clock signals 308, 310, and 312 relative to oneanother and relative to the input signal 306, as further illustrated inFIG. 3 and explained below, output signals generated based upon theinput signal 306 and the clock signals 308, 310, and 312 are effectivelyidentical or substantially identical. More particularly, in the firstgraph 300, it can be seen that a first output signal 322 is step-shapedand includes a series of steps 324, that a first step 326 of the seriesof steps 324 occurs a first time differential 328 after the time 320,and that the series of steps has an effective slope represented by adashed line 330. Each of the steps 324 has a respective leading edgethat occurs simultaneously or substantially simultaneously with acorresponding rising edge of the first clock signal 308 subsequent tothe time 320. Thus, each of the steps 324 has the same or substantiallythe same width corresponding to the period of the first clock signal308.

By comparison, in the second graph 302, it can be seen that a secondoutput signal 332 also is step-shaped and includes a series of steps334, that a first step 336 of the series of steps 334 occurs a secondtime differential 338 after the time 320, and that the series of stepshas an effective slope represented by a dashed line 340. Similar to thesteps 324, each of the steps 334 has a respective leading edge thatoccurs simultaneously or substantially simultaneously with acorresponding rising edge of the second clock signal 310 subsequent tothe time 320. Thus, each of the steps 334 has the same or substantiallythe same width corresponding to the period of the second clock signal310. Additionally by comparison, in the third graph 304, it can be seenthat a third output signal 342 also is step-shaped and includes a seriesof steps 344, that a first step 346 of the series of steps 344 occurs athird time differential 348 after the time 320, and that the series ofsteps has an effective slope represented by a dashed line 350. Similarto the steps 324 and 334, each of the steps 344 has a respective leadingedge that occurs simultaneously or substantially simultaneously with acorresponding rising edge of the third clock signal 312 subsequent tothe time 320. Thus, each of the steps 344 has the same or substantiallythe same width corresponding to the period of the third clock signal312.

Inspection of the first, second, and third output signals 322, 332, and342 shows that those three output signals do differ from one another incertain respects. In particular, it should be appreciated that, althougheach of the first steps 326, 336, and 346 are identical or substantiallyidentical in width (e.g., in temporal extent), the first step 326 of thefirst output signal 322 is shorter in height than the first step 336 ofthe second output signal 332, and each of the first and second steps 326and 336 of the first and second output signals 322 and 332,respectively, is shorter in height than the first step 346 of the thirdoutput signal 342. This is in contrast to the heights of subsequentsteps 356, 366, and 376, respectively, of the first, second, and thirdoutput signals 322, 332, and 342, respectively, all of which are shownto be identical to one another in terms of their height (relative to thepreceding step) and width.

Yet notwithstanding the differences of the heights of the respectivefirst steps 326, 336, and 346 of the first, second and third outputsignals 322, 332, and 342, respectively, it should additionally beappreciated that the dashed lines 330, 340, and 350, are all identicalor substantially identical. More particularly, it should be appreciatedthat first, second, and third virtual starting points 352, 362, and 372,respectively, through which the dashed lines 330, 340, and 350respectively pass, not only are respectively aligned with respectiveinitial (zero) levels 354, 364, and 374 of the first, second, and thirdoutput signals 322, 332, and 342, respectively, but also are all aligned(or substantially aligned) in time with the time 320 at which the inputsignal 306 experiences a zero crossing. Further, it should also beappreciated that the dashed lines 330, 340, and 350, which effectivelyrepresent the respective slopes of the first, second, and third outputsignals 322, 332, and 342, respectively, all have an identical orsubstantially identical slope. Thus, in terms of their virtual startingpoints 352, 362, and 372 and their trajectories represented by thedashed lines 330, 340, and 350, the first, second, and third outputsignals 322, 332, and 342 are substantially identical to one another.Relatedly, to the extent that the dashed lines 330, 340, and 350 areconsidered to be the true output signals (rather than the signals 322,332, and 342), all of those output signals are identical orsubstantially identical.

From FIG. 3, it should additionally be recognized that the first,second, and third output signals 322, 332, and 342 are substantiallyidentical to one another, and that the dashed lines 330, 340, and 350are identical or substantially identical to one another, because of theparticular characteristics of the steps 324, 334, and 344. As shown, thefirst steps 326, 336, and 346 of FIG. 3 occur in time subsequent to thetime 320 and particularly step up (e.g., have rising edges) at the sameor substantially the same times, respectively, as respective risingedges of the respective clock signals 308, 310, and 312 first occurafter the time 320. However, the heights of the first steps 326, 336,and 346 respectively have varying values that are related to the extentof the time differentials 328, 338, and 348, respectively. The heightsare particularly set so that the slopes of the dashed lines 330, 340,and 350 are identical or substantially identical to one another as thosedashed lines extend from the respective virtual starting points 352,362, and 372, respectively, to respective leading top corners 358, 368,and 378 of the first steps 326, 336, and 346, respectively.

Further, the respective slopes of the respective dashed lines 330, 340,and 350 established by the respective virtual starting points 352, 362,and 372 and the respective leading top corners 358, 368, and 378 alsoare consistent with subsequent steps 356, 366, and 376, respectively, ofthe output signals 322, 332, and 342, respectively. Indeed, as shown,the respective dashed lines 330, 340, and 350 not only extend from therespective virtual starting points 352, 362, and 372 to the respectiveleading top corners 358, 368, and 378, respectively, but also extendwithout any change in their slopes to successive leading top corners360, 370, and 380, respectively, of the subsequent steps 356, 366, and376, respectively.

The heights of first steps of output signals such as the first steps326, 336, and 346 can be calculated in a variety of manners dependingupon the embodiment. In the present embodiment of FIG. 3, in which it isassumed that there are high oversampling ratios, the input signal 306can be assumed to be linear between sampling moments around the zerocrossing, where the sampling moments are times coinciding with therising edges of the clock signal at which the input signal is sampled.For example, with respect to the first graph 300, the sampling momentsaround the zero crossing include a time 384 coinciding with the risingedge of the first clock signal 308 preceding the time 320 at which azero crossing occurs that is closest to that time 320, and also a time386 coinciding with the rising edge of that clock signal occurringsubsequent to the time 320 that is closest to that time 320.

Using these sampled moments and the aforementioned assumption oflinearity, the clock phase can be calculated based upon the sampledvalue at the time 384 just before the zero crossing (X_(n-1)) and thesampled value at the time 386 just after the zero crossing (X_(n)), asX_(n)/(X_(n)−X_(n-1)). Further, with such a known (calculated) clockphase determined based upon X_(n) and X_(n-1), an adjusted height 390 ofthe first step 326 used by the DAC, represented by a variableLSB_(first) (first Least Significant Bit) can be calculated based uponthe clock phase and a standard height 388 of the subsequent steps 356 ofthe output signal 322, represented by a variable LSB_(nom) (nominalLeast Significant Bit) by way equation (1) as follows:LSB_(first) =X _(n)/(X _(n) ×X _(n-1))·LSB_(nom)  (1).

Although corresponding sample moments before and after the zero crossingat the time 320, and adjusted and standard heights corresponding to theadjusted height 390 and standard height 388 of the first graph 300, arenot labeled with reference numerals in the second graph 302 and 304,nevertheless the adjusted heights of the first steps 336 and 346 can becalculated in the same manner as described above using equation 1. Inparticular, it should be appreciated that the standard heights of thesubsequent steps 366 and 376 in the present example are identical orsubstantially identical to the standard height 388. Further, the samplevalues X_(n-1) and X_(n) in the case of the graph 302 will be the valuesof the input signal 306 at the sample moments coinciding with the risingedges of the clock signal 310 that are closest to the time 320,respectively preceding and occurring subsequent to the time 320.Likewise, the sample values X_(n-1) and X_(n) in the case of the graph304 will be the values of the input signal 306 at the sample momentscoinciding with the rising edges of the clock signal 312 that areclosest to the time 320, preceding and occurring subsequent to the time320. Notwithstanding the above description, it should also beappreciated that, in alternate embodiments, other (e.g., non-linear)interpolation techniques can also be used.

Thus, FIG. 3 illustrates a manner of operation in which, by virtue ofemploying a variable first DAC step, the virtual starting point of theeffective slope of the output signal can be perfectly (or substantiallyperfectly) aligned with the actual zero crossing of the input signal.Consequently, even though the timing (and relative phases) of the first,second, and third clock signals 308, 310, and 312 are different from oneanother, the first, second and third output signals 322, 332, and 342still are identical or substantially identical. Therefore, assumingoperation of the pulse-shaping DAC 202 occurs in this manner, variationin the timing or phase of a clock signal (e.g., so that the clock signaltakes on, at different times, the different timing of the clock signals308, 310, and 312) does not result in corresponding phase variation, orjitter, in the resulting output signal. To the contrary, the resultingoutput signal retains the same or substantially the same timing or phaserelative to the input signal 306, and particularly relative to zerocrossings of the input signal 306 such as that illustrated at the time320, regardless of variations in the timing or phase of the clock signalused to generate that output signal.

Although not shown in FIG. 3, it should be appreciated that the outputsignals 322, 332, and 342 (and corresponding dashed lines 330, 340, and350, respectively) do not continue indefinitely upward, with an endlessnumber of ongoing ones of the subsequent steps 356, 366, and 376,respectively. Rather, at some point within the given period (orhalf-period) of the input signal 306 that began at the time 320, theoutput signals 322, 332, and 342 return to the respective initial (zero)levels 354, 364, and 374, so as to be reset. Then, subsequently, at anext time corresponding to the next zero-crossing of the input signal306, the output signals 322, 332, and 342 can again experience firststeps having adjusted heights as described above, followed by subsequentsteps having standard heights. Given this to be the case, it should befurther appreciated that (though not shown in FIG. 3) each of the outputsignals 322, 332, and 342 has a respective final step, prior toreturning to the respective initial level 356, 364, and 374. In at leastsome embodiments, this final step can have a height that differs fromthe standard height 388. In other words, because the first DAC step hasa variable height, also the last DAC step can be adjustable, forexample, to achieve an end value (e.g., highest value) of the outputsignal that is at a particular desired level. For example, in some suchembodiments, each respective final step can have a height that is equalto the difference between the standard height and the adjusted height ofthe preceding first step, so that the overall rise in the output signalfrom its initial level to its final level is a multiple of the standardheight. Further for example, with respect to the output signal 322 ofthe first graph 300, the height of the final step of that output signalprior to its returning to the initial level 354 can be equal to thedifference between the standard height 388 and the adjusted height 390.The standard height 388, and correspondingly the adjusted height 390 aswell as the difference between the standard and adjusted heights, canhave a variety of values depending upon the embodiment. For example, insome embodiments, consistent with some speed sensor applications and inaccordance with the AK protocol, supply current steps (e.g.,corresponding to the standard height 388) from 7 mA (milliAmperes) to 14mA, or from 7 mA to 28 mA, can occur after a zero-crossing is detected.

Turning to FIGS. 4, 5, 6, and 7, as mentioned above, the DAC 202 of FIG.2 can take any of a variety of forms depending upon the embodiment, andthe present disclosure is intended to encompass numerous differentembodiments of such a device (or system or circuit component). Severalsuch example embodiments are shown in each of FIG. 4, FIG. 5, FIG. 6,and FIG. 7 herein. As described in further detail below, the embodimentsof pulse-shaping DACs shown in FIG. 4 and FIG. 6 are embodiments havingtopologies that are current domain topologies. By comparison, theembodiments of FIGS. 5 and 7 are embodiments having topologies that arevoltage domain topologies. Notwithstanding the particular exampleembodiments of pulse-shaping DACs shown in FIGS. 4, 5, 6, and 7, thepresent disclosure is intended to encompass numerous other alternateembodiments of pulse-shaping DACs as well.

In the example embodiment shown in FIG. 4, the output DAC 202 takes theform of a current domain DAC 400 that is constructed directly in thecurrent domain. As shown, the current domain DAC 400 includes a smallfixed current source 402, a N-channel metal oxide semiconductor fieldeffect transistor (MOSFET) 404, an operational amplifier 406, a voltagesource 408, a switchable current source 410, a plurality of additionalcurrent sources 412, and a plurality of switches 414.

As shown, the voltage source 408 is coupled between a ground terminal416 and a non-inverting terminal 418 of the operational amplifier 406.An output terminal 420 of the operational amplifier 406 is coupled tothe gate of the MOSFET 404, and an inverting terminal 422 of theoperational amplifier is coupled to a source of the MOSFET 404. Theinverting terminal 422 and source of the MOSFET 404 can be considered toform a node 403. As further shown, the current source 402 is coupled tothe node 403, between that node and the ground terminal 416, and drivesa biasing current I_(bias). Additionally, a first switch 424 of theplurality of switches 414 is coupled between the node 403 and theswitchable current source 410, which is coupled between the first switch424 and the ground terminal 416. Given this arrangement, the firstswitch 424 and switchable current source 410 together constitute acomponent that is coupled in parallel with the current source 402, andthe switchable current source 410 particularly can be coupled inparallel with or decoupled from (so as to not be coupled in parallelwith) the current source 402 depending upon the status of the firstswitch 424.

Additionally as shown, the plurality of switches 414 not only includesthe first switch 424 but also includes one or more additional switches426 that, in the present example embodiment, include a first additionalswitch 428 and a second additional switch 430. In general, each of theadditional switches 426 is coupled in series with a respective one ofthe additional current sources 412 that each is configured to drive acurrent I_(LSB) and that, in the present example embodiment, include afirst additional current source 432 and a second additional currentsource 434. More particularly as shown, the series-coupled firstadditional switch 428 and first additional current source 432 togetherconstitute a component that is coupled in parallel with the switchablecurrent source 410, between the ground terminal 416 and the node linkingthe first switch 424 and the switchable current source 410. Similarly,the series-coupled second additional switch 430 and second additionalcurrent source 434 together constitute a component that is coupled inparallel with the first additional current source 432, between theground terminal 416 and the node linking the first additional switch 428and the first additional current source 432. Given this arrangement, itwill be appreciated that, depending upon the actuation of the firstswitch 424, the first additional switch 428, and the second additionalswitch 430, the current source 402 not only can be operated in parallelwith the switchable current source 410 alone but also can be operated inparallel with either the first additional current source 432 or both thefirst and second additional current sources 432 and 434.

Although the embodiment of FIG. 4 particularly shows two of theadditional switches 426 and two of the additional current sources 412,in other embodiments there can be any arbitrary number (one or more) ofthese additional switches and current sources. Dashed lines 436 shown inFIG. 4 particularly are provided to illustrate that it is envisionedthat, in at least some embodiments, more than two of the additionalswitches 426 and more than two of the additional current sources 412 arepresent. As shown, the dashed lines 436 particularly link the secondadditional current source 434 to the node of the first additionalcurrent source 432 that is coupled to the ground terminal 416, and linkthe second additional switch 430 to the node linking the firstadditional switch 428 and the first additional current source 432. Thus,the dashed lines 436 are intended to indicate that one or more circuitportions or components including a respective series-coupled additionalswitch and additional current source can be coupled in between theseries-coupled first additional switch 428 and first additional currentsource 432 or in between the series-coupled second additional switch 430and second additional current source 434.

In the present embodiment, the switchable current source 410 can bedynamically scaled to the clock phase. That is, a switchable currentI_(SW) can be modified to take on a variety of values in accordance withclock phase. By contrast, each of the additional current sources 412drives a current I_(LSB) of fixed value. Thus, depending upon theactuation of the switches 414, the current driven between the groundterminal 416 and the node 403 can be any of I_(bias), I_(bias) plusI_(SW), I_(bias) plus I_(SW) and I_(LSB), and I_(bias) plus each ofI_(SW) and two times I_(LSB). Additionally, in alternate embodiments thenumber of each of the additional current sources 412 and the associatedadditional switches 426 can be a number n other than two. In suchembodiments, depending upon the actuation of the switches 414, thecurrent driven between the node 403 and the ground terminal 416 can beany of I_(bias), I_(bias) plus I_(SW), and I_(bias) plus each of I_(SW)and n times I_(LSB), where n can take on each of any value 1 to n. Itshould be appreciated that the operational amplifier 406 is provided tokeep the voltage across the current sources constant, which will relaxthe specification on the output resistance of the current sources (withthe voltage being defined by the voltage source 408).

Based upon a comparison of FIG. 3 and FIG. 4, it should be appreciatedthat the circuit of FIG. 4 is capable of operating to generate an outputsignal I_(out) that corresponds to any of the output signals 322, 332,and 342, and that this is achieved by varying the value of I_(SW) andthe timing of the actuation of the switches 414 depending upon the phaseof the clock signal. More particularly, the value of I_(SW) and thetiming of the closing of the first switch 424 are set or modified sothat the combination of I_(SW) and I_(bias) can produce a first step inthe output signal I_(out) that is consistent with having a virtualstarting point that occurs at the time 320, regardless of the timing ofthe clock signal. For example, in order to achieve the output signals322, 332, and 342, respectively, notwithstanding variation in the clocksignal among the clock signals 308, 310, and 312, respectively, thefirst switch 424 is actuated to be closed at three different timescorresponding to the time differentials 328, 338, and 348 occurringafter the time 320 so as to couple the switchable current source 410 inparallel with the current source 402. With such actuation at those threedifferent times associated with the time differentials 328, 338, and348, respectively, the respective output signals 322, 332, and 342 takeon the values of the first steps 326, 336, and 346, respectively.

Subsequent to the actuation of the first switch 424, the additionalswitches 426 are then successively actuated so as to be closed atappropriate times corresponding to the successive leading edges of theclock signal. By virtue of the successive closing of the additionalswitches 426, successive currents provided by the respective additionalcurrent sources 412 each in the amount of I_(LSB) are added to thecombination of I_(SW) and I_(bias) so as to generate subsequent steps ofthe output signal I_(out). For example, in regard to the example of FIG.3, the successive closing of the additional switches 424 results in theoccurring of the subsequent steps 356, 366, or 376, respectively,depending upon whether the clock signal has the phase of the clocksignal 308, the clock signal 310, or the clock signal 312, respectively.It should be appreciated that the number of subsequent steps that occurfollowing a first step of the output signal can generally match thenumber of additional switches and corresponding additional currentsources that are present in a DAC such as the DAC 400. Therefore, theDAC 400 as particularly shown in FIG. 4 with two of the additionalcurrent sources 412 and two of the additional switches 426 (and ignoringthe implications of the dashed lines 436) is configured to produceoutput signals having three steps. Alternatively, to achieve operationin which each of the subsequent steps 356, 366, or 376 of the outputsignals 322, 332, or 342, respectively, include more than two steps(e.g., at least three steps), in actuality the DAC 400 will include morethan two (e.g., at least three) of the additional switches 426 and morethan two of the additional current sources 412.

Although not shown in FIGS. 3 and 4, it should further be understoodthat, in at least some embodiments, it will be desired that the outputsignal attain (or not surpass) a maximum value (or consistent end value)prior to returning to an initial value. For example, it may be desiredthat such a maximum value of the output signal I_(out) occurs when acurrent equaling the sum of I_(bias) and three times I_(LSB) flowsbetween the node 403 and the ground terminal 416. To achieve suchdesired behavior, a modified version of the DAC 400 of FIG. 4 can beappropriate. More particularly, to achieve such desired behavior, theadditional current sources 412 will include a final (in this example,third) current source in addition to the additional current sources 432,434, and the additional switches 426 will include a final (in thisexample, third) switch in addition to the additional switches 428, 430.In such embodiment, the series-connected final switch and final currentsource will be coupled in parallel with the current source 434, betweenthe ground terminal 416 and the node linking the additional switch 430and the additional current source 434. Further, the final current sourcewill be an additional switchable current source (rather than a fixedcurrent source) that is configured to generate a final current I_(FIN)that is equal to I_(LSB) minus I_(SW). Notwithstanding this particularexample embodiment, in other embodiments, the maximum value of theoutput Iout can be any arbitrary number or value, and the number ofadditional switches and additional current sources and the exact currentgeneration provided by any final current source can be modified toachieve such maximum value.

The DAC 400 is a “current domain” arrangement in that control over theoutput signal I_(out) is determined by governing the amount of currentflowing between the node 403 and the ground terminal 416. Nevertheless,the DAC 202 can also take the form of a “voltage domain” arrangement.One example of such an arrangement is a DAC 500 shown in FIG. 5. In thisexample, the DAC 500 includes a biasing current source 502, a N-channelMOSFET 504, an operational amplifier 506, an output resistor 508 with aresistance R_(out), a base resistor 509, a switchable or variableresistor 510, a plurality of additional resistors 512, and a pluralityof switches 514. As shown, the base resistor 509 and the output resistor508 are both coupled to a ground terminal 516. Further, the operationalamplifier 506 includes a non-inverting terminal (or port) 518, an outputterminal 520 and an inverting terminal 522, where the output terminal520 is coupled to the gate of the MOSFET 504. Also, a node 503 links thesource of the MOSFET 504 with each of the inverting terminal 522 and theoutput resistor 508, which is coupled between the node 503 and theground terminal 516. A current I_(out) flowing with respect to the drainof the MOSFET 504 constitutes the output current of the DAC 500 and canbe considered the output signal of the DAC that corresponds for exampleto any of the output signals 322, 332, and 342 of FIG. 3.

As further shown, the base resistor 509, switchable resistor 510, andeach of the resistors of the plurality of additional resistors 512 arecoupled in series with one another between the ground terminal 516 andthe biasing current source 502. The base resistor 509 particularly iscoupled between the switchable resistor 510 and the ground terminal 516,and the switchable resistor 510 is coupled between the base resistor 509and a first additional resistor 532 of the plurality of additionalresistors 512. The first additional resistor 532 is coupled between asecond additional resistor 534 of the plurality of additional resistors512, which in turn is coupled between the first additional resistor 532and the biasing current source 502. Additionally, each of the switches514 is coupled between a respective node linking a respective pair ofthe resistors 509, 510, and 512 and the non-inverting input terminal 518of the operational amplifier 518.

More particularly, a first switch 524 of the switches 514 is coupledbetween node linking the base resistor 509 and the switchable resistor510 and the non-inverting input terminal 518. Additional switches 526 inturn are coupled between others of the nodes between the resistors 510and 512 and the non-inverting terminal 518. More particularly, a firstadditional switch 528 of the additional switches 526 is coupled betweenthe non-inverting terminal 518 and the node linking the switchableresistor 510 and the first additional resistor 532, a second additionalswitch 529 of the additional switches 526 is coupled between thenon-inverting terminal 518 and the node of the first additional resistor532 that is linked to the second additional resistor 534, a thirdadditional switch 530 of the additional switches 526 is coupled betweenthe non-inverting terminal 518 and the node of the second additionalresistor 534 that is linked to the first additional resistor 532, and afourth additional switch 531 of the additional switches 526 is coupledbetween the non-inverting terminal 518 and the node linking the secondadditional switch 534 and the biasing current source 502.

Additionally, dashed lines 536 are shown to couple the aforementionednodes of the first and second additional resistors 532, 534 to which thesecond and third additional switches 529, 530 are coupled, and to couplethe opposite terminals of those second and third additional switches529, 530 so that both of those switches are coupled to the non-invertingterminal 518. The presence of the dashed lines 536 is intended tosignify that any arbitrary number n of the additional resistors 512 (andparticularly any arbitrary number n>1) can be present depending upon theembodiment, and also to signify that correspondingly any arbitrarynumber n>2 (or alternatively n>1) of the additional switches 526 can bepresent depending upon the embodiment.

Given this arrangement, the DAC 500 also can serve the same orsubstantially the same purpose as the DAC 400 in terms of generating theoutput signal I_(out) in a manner that does not vary (or substantiallyvary) depending upon the timing or phase of the clock signal. Althoughthe base (lowest) resistor 509 merely serves a purpose of biasing theMOSFET (output transistor) 504 with a minimum current, the switchableresistor 510 allows for variations in the first step of the outputsignal, and corresponding variations in the virtual starting point ofthe output signal (such as the virtual starting points 352, 362, and372). More particularly, in this embodiment employing a switch matrixinvolving the switches 514, the voltage on the non-inverting (positive)input terminal 518 of the operational amplifier 506 can be selectedthrough variation in the resistance provided by the switchable resistor510 and actuation (closing and opening) different ones of the switches514. Due to the high gain of the operational amplifier 506, the voltageon the output resistor 508 (with the resistance R_(out)) will be equalto the selected voltage. In turn, the output signal I_(out) will beproportional to the reference current 502 (and scale with the selectedvoltage).

In particular, an initial value of the output signal I_(out) occurs whenthe first switch 524 is closed (short-circuited) and all of the othersof the switches 514 are opened (open-circuited). Additionally, a firststep in the output signal I_(out) such as any of the first steps 326,336, and 346 of FIG. 3 can occur when it is the first additional switch528 that is closed and all of the others of the switches 514 are opened.Further, subsequent steps of the output signal I_(out) such as any ofthe subsequent steps 356, 366, and 376 of FIG. 3 can occur as other onesof the additional switches 526 are closed while all of the others of theswitches 514 are opened.

Additionally, although not shown in FIGS. 3 and 5, it should again beunderstood that, in at least some embodiments, it will be desired thatthe output signal attain (or not surpass) a maximum value (or consistentend value) prior to returning to an initial value. To achieve suchdesired behavior, a modified version of the DAC 500 of FIG. 5 can beappropriate. More particularly, to achieve such desired behavior, theadditional resistors 512 will include a final (in this example, third)additional resistor in addition to the additional resistors 532, 534,and the additional switches 526 will include a final (in this example,fifth) additional switch to supplement the additional switches 528, 529,530, 531. In such embodiment, the final additional resistor will becoupled between the current source 502 and the second additionalresistor 534, and the final additional switch will be coupled betweenthe non-inverting terminal 518 and the node linking that current sourceand final additional resistor. Further, in such embodiment, the finalresistor will be an additional switchable or variable resistor (ratherthan a fixed resistor) that is adjustable to the phase of the clock. Itshould be appreciated that the maximum value of the output currentI_(out) can be any arbitrary number or value, and the number ofadditional resistors and additional switches, as well as the degree towhich the final resistor can be varied in terms of its resistance, canbe modified to achieve such maximum value.

Turning to FIG. 6 and FIG. 7, respectively, additional schematicdiagrams show further examples of the DAC 202, namely, a DAC 600 and aDAC 700, respectively. It should be appreciated that the DAC 600 of FIG.6 is similar to the DAC 400 of FIG. 4 in that it is a current domainarrangement, and that the DAC 700 of FIG. 7 is similar the DAC 500 ofFIG. 5 in that it is a voltage domain arrangement. As such, many of thecomponents of the DAC 600 are identical, substantially similar, oranalogous to many of the components of the DAC 400, and likewise many ofthe components of the DAC 700 are identical, substantially similar, oranalogous to many of the components of the DAC 500. At the same time,the DACs 600, 700 of FIGS. 6 and 7 show in greater detail certaincontrol components, including a plurality of decoders and flip-flops(FFs), which can be employed to control the timing of the opening andclosing of switching components that are present in the DACs. Suchcontrol components are merely exemplary and, in other embodiments, othertypes of control components or circuitry (e.g., a microprocessor) can beemployed. Although not shown in FIGS. 4 and 5, it should be recognizedthat the DACs 400 and 500 also will typically be operated in conjunctionwith, and controlled by way of, control components or circuitry such asthat of FIGS. 6 and 7 or otherwise.

More particularly as shown, the DAC 600 has a N-channel MOSFET 604 andan operational amplifier 606 that are (or can be) identical to theMOSFET 404 and operational amplifier 406. In this arrangement, a currentI_(out) flowing in relation to a drain of the MOSFET 404 is the outputsignal of the DAC, an output terminal 620 of the operational amplifier606 is coupled to a gate of the MOSFET 604, and a node 603 links aninverting terminal 622 of the operational amplifier with a source of theMOSFET 604. A non-inverting terminal 618 of the operational amplifier606 is coupled to a ground terminal 616 by way of a resistor 608, and acurrent source 609 also coupled to the non-inverting terminal 618 drivesa current through the resistor 608 so as to produce a voltage on thenon-inverting terminal such that the arrangement of the resistor 608 andcurrent source 609 can be considered analogous to the voltage source 408of FIG. 4. A biasing current corresponding to the current I_(bias) ofFIG. 4 is provided by the coupling of a resistor 602 with a resistanceR_(bias) between the node 603 and the ground terminal 616.

Additionally, a subcircuit 610 is also coupled in parallel with theresistor 602 between the node 603 and the ground terminal 616 and servesthe role of the switchable current source 410 of FIG. 4. In theembodiment of FIG. 6, the subcircuit 610 particularly is formed by thecombination of four switchable resistors 611 and four series-connectedswitches 613. As shown, each of the switchable resistors 611 is coupledbetween the ground terminal 616 and the node 603 by way of a respectiveone of the series-connected switches 613, with the switch beingconnected between the node 603 and the respective resistor. Theresistance of each of the switchable resistors 611 can be an arbitrarynumber, and in some embodiments the resistances of the differentresistors can be of equal value or take on different values, although inthe present embodiment the resistances are all equal (shown as 4 R).

Control of the switching (closed/open) status of each of the switches613 causes the respective switchable resistors 611 to be coupled inparallel with the resistor 602 or decoupled from the node 603, such thatthe effective resistance provided by the subcircuit 610 can be varied.Correspondingly, the current flowing through the subcircuit 610 can bevaried, and can be considered a switchable current corresponding to thecurrent I_(SW) of FIG. 4. It is noteworthy that, in the embodiment ofFIG. 6 in which each of the resistors 611 is individually associatedwith a respective one of the switches 613, there is no further switchpresent in between the node 603 and the switches 613 of the subcircuit610 that would specifically correspond to the switch 424 of FIG. 4.Rather, the switches 613 can be understood as serving both the purposeof the switch 424, in terms of controlling timing or actuation, as wellas allowing for and governing the variation in the current passingthrough the subcircuit 610.

In addition, the DAC 600 also includes a plurality of (again, in thisexample, two) additional switches 626 and a plurality of (in thisexample, two) additional resistors 612. In the present exampleembodiment, a first additional resistor 632 of the additional resistors612 is coupled in series between the ground terminal 616 and a firstadditional switch 628 of the additional switches 626, which is coupledbetween the first additional resistor 632 and the node 603. Also, asecond additional resistor 634 of the additional resistors 612 iscoupled in series between the ground terminal 616 and a secondadditional switch 630 of the additional switches 626, which is coupledbetween the second additional resistor and the node linking the firstadditional resistor 632 with the first additional switch 628. Due tothis arrangement, depending upon whether none of the additional switches626, or only the first additional switch 628, or both of the first andsecond additional switches 628, 630 are closed, none of the additionalresistors 612, the first additional resistor 632, or both of the firstand second additional resistors 632, 634 are coupled in parallel withthe subcircuit 610 and the resistor 602.

The resistance of each of the additional resistors 612 can be anarbitrary number, and in some embodiments the resistances of theseresistors can be of equal value or take on different values. However, inthe present embodiment, the resistances of each of the resistors 612 areall equal (shown as R), and as a consequence the currents that flowthrough each of the resistors 612 when any of those resistors is coupledin parallel with the resistor 602 are identical (as dependent upon thevoltage at the node 603) and can be viewed as corresponding to thecurrents I_(LSB) driven by each of the current sources of FIG. 4. Also,given that in the present example embodiment each of the additionalresistors 612 has a resistance R and each of the resistors 611 has aresistance 4 R, the current flowing through either of the additionalresistors 612 when a corresponding one of the additional switches 626 isclosed will be equal to the sum of the currents that will flow throughthe subcircuit 613, through all four of the resistors 611, if all fourof those resistors are conductive due to all four of the switches 613being closed.

More generally, it will be appreciated from a comparison of the DAC 600of FIG. 6 and the DAC 400 of FIG. 4 that the combination of the firstadditional switch 628 and the first additional resistor 632 operates inthe same or substantially the same manner as the combination of thefirst additional switch 428 and the first additional current source 432of FIG. 4. Likewise, the combination of the second additional switch 630and the second additional resistor 634 operates in the same orsubstantially the same manner as the combination of the secondadditional switch 430 and the second additional current source 434.Also, as with the embodiment of FIG. 4, FIG. 6 also shows dashed lines636 (corresponding to the dashed lines 436 of FIG. 4), which indicatethat, although only two each of the additional switches 626 andadditional resistors 612 are shown, in other embodiments orimplementations any arbitrary number of those switches and resistors canbe present.

In addition to the above-discussed aspects, the DAC 600 additionallyincludes a further subcircuit 640 that is coupled in parallel with thesecond additional resistor 634, between the ground terminal 616 and anode 638 linking that one of the additional resistors with the secondadditional switch 630. In the present embodiment, the subcircuit 640includes four switchable resistors 641 and four switches 643. As shown,each of the switches 641 is coupled between the ground terminal 616 andthe node 638 by way of a respective one of the switches 643 (with theswitch being connected between the node 638 and the respectiveresistor). The resistance of each of the switchable resistors 641 can bean arbitrary number, and in some embodiments the resistances of thedifferent resistors can be of equal value or take on different values,although in the present embodiment the resistances are all equal (shownas 4 R). Control of the switching (closed/open) status of each of theswitches 643 causes the respective switchable resistors 641 to becoupled to or decoupled from the node 638, such that the effectiveresistance provided by the subcircuit 640 can be varied.

Further in addition to the above aspects, FIG. 6 also shows controlcircuit components 648 of the DAC 600 that are employed to controloperation of the DAC, and particularly are employed to control theopening and closing—including the timing of such opening and closing—ofthe switches 613, 626, and 643. More particularly as shown, the controlcircuit components 648 include first, second and third input ports 650,652, and 654, respectively, at which are provided a clock signal 656, azero-crossing signal 658, and a phase signal 660. The clock signal 656can (but need not) include or correspond to any of the clock signals308, 310, or 312 of FIG. 3. The zero-crossing signal 658 can (but neednot) include or correspond to the input signal 306 of FIG. 3. The phasesignal (or signals) 658 can be utilized to indicate the input phase ofthe input signal such as the input signal 306.

Additionally as shown, the control circuit components 648 includes aplurality of flip-flops (FFs) 662 that, in the present example,particularly include first, second, third, and fourth flip-flops 664,666, 668, and 670, respectively. As indicated by additional ones of thedashed lines 636, the number of the flip-flops 662 that are present willcorrespond in part to the number of the additional switches 626 and, inthe present example, will exceed the number of the additional switches626 by two. As shown, the first input port 650 is tied to each offlip-flops 662. Further, the second input port 652 is coupled to thefirst flip-flip 664, which in turn is coupled by a first link 672 to thesecond flip-flip 666, which in turn is coupled by a second link 674 tothe third flip-flop 668, which in turn is coupled by a third link 676 tothe fourth flip-flop 670.

Additionally, the control circuit components 648 also include a firstdecoder 678 and a second decoder 680. As shown, the third input port 654is coupled to each of the first and second decoders 678, 680. Further,the first link 672 also connects each of the first and second flip-flops664 and 666 with the first decoder 678, and an additional link 682couples the fourth flip-flop 670 with the second decoder 680. Further asillustrated by control lines 686, the first decoder 678 controls theopen/closed status of each of switches 613 and, as illustrated bycontrol lines 688, the second decoder 680 control the open/closed statusof each of the switches 643. The second link 674 further couples thesecond and third flip-flops 666, 668 with the switch 628 such that theoutput of the second flip-flop 666 governs the open/closed status ofthat switch, and the third link 676 couples the third and fourthflip-flops 668, 670 with the switch 630 such that the output of thethird flip-flop 668 governs the open/closed status of that switch.

Based upon a comparison of FIG. 3 and FIG. 6, it should be recognizedthat the circuit of FIG. 6 is capable of operating to generate an outputsignal I_(out) that corresponds to any of the output signals 322, 332,and 342, and that this is achieved by appropriate actuation of theswitches 613, 626, and 643 depending upon the phase of the clock signal656. More particularly, based upon the phase of the clock signal 656,the first decoder 678 causes the switches 613 to be opened or closed inan appropriate manner so as to establish an additional current flowsupplementing the baseline current passing through the resistor 602.Such actuation of the switches 613 results in a first step in the outputsignal I_(out) that is consistent with having a virtual starting pointthat occurs at the time 320, regardless of the timing of the clocksignal. Subsequently, the switches 626 in sequential order based upontheir proximity to the node 603 (e.g., the first switch 628 followed bythe second switch 630) are actuated so as to be closed, which furthersupplements the current flowing between the node 603 and the groundterminal 616, and consequently results in subsequent steps in the outputsignal I_(out) that are respectively consistent with the subsequentsteps 356, 366, and 376 of FIG. 3.

Further, as already discussed above in regard to FIGS. 3, 4, and 5, inat least some embodiments it will be desired that the output signalattain (or not surpass) a maximum value (or consistent end value) at alast step prior to returning to an initial value. The second decoder 680governs actuation of the switches 643 of the further subcircuit 640 andallows for such desired behavior to be achieved. More particularly,based upon the actuation of the switches 643, an additional current flowoccurs between the node 603 and the ground terminal 616 that results ina further increase in the output signal I_(out). In the present example,the switches 643 are actuated so that the additional current flowbetween the node 603 and the ground terminal 616 via the furthersubcircuit 640 is equal to the difference between the increase in theoutput signal that occurs due to the flowing of current through eitherone of the resistors 626 and the increase in the output signal thatoccurs due to the flowing of current between the node 603 and the groundterminal 616 by way of the subcircuit 610.

To achieve such example operation, the further subcircuit 640 can becontrolled to operate in a manner that is effectively the inverse of theoperation of the subcircuit 610. For example, in the event that one ofthe four resistors 611 of the subcircuit 610 is controlled to beconductive (e.g., because one of the four switches 613 is closed), thenin such case three out of the four resistors 641 of the furthersubcircuit 640 will ultimately, at the time of the final step, be causedto be conductive (e.g., because three of the four switches 643 areclosed), and vice-versa. Notwithstanding this particular exampleembodiment, in other embodiments, the maximum value of the outputI_(out) can be any arbitrary number or value, and the numbers andresistance values of the switches and resistors that are present ineither of the subcircuits 610 and 640 can be modified to achieve suchmaximum value. Further, the actuation of the switches in suchsubcircuits need not be inverted as described above in some otherembodiments.

Turning to FIG. 7, the DAC 700 is an arrangement that is similar in manyrespects to the DAC 500 of FIG. 5. Among other things, the DAC 700 has aN-channel MOSFET 704 and an operational amplifier 706 that are (or canbe) identical to the MOSFET 504 and operational amplifier 506. Similarto the embodiment of FIG. 5, the DAC 700 also includes an outputresistor 708 with a resistance R_(out), a base resistor 709, a pluralityof additional resistors 712, a plurality of switches 714, and a currentsource 702, which respectively can be considered as corresponding to theoutput resistor 508, base resistor 509, plurality of additionalresistors 512, plurality of switches 514, and current source 502,respectively. As shown, the base resistor 709 and the output resistor708 are both coupled to a ground terminal 716. Further, the operationalamplifier 706 includes a non-inverting terminal 718, an output terminal720 and an inverting terminal 722, where the output terminal 720 iscoupled to the gate of the MOSFET 704. Also, a node 703 links the sourceof the MOSFET 704 with each of the inverting terminal 722 and the outputresistor 708, which is coupled between the node 703 and the groundterminal 716. A current I_(out) flowing with respect to the drain of theMOSFET 704 constitutes the output current of the DAC 700 and can beconsidered the output signal of the DAC that corresponds for example toany of the output signals 322, 332, and 342 of FIG. 3.

As further shown, the base resistor 709 and each of the resistors of theplurality of additional resistors 712 are coupled in series with oneanother between the ground terminal 716 and the biasing current source702. In contrast to the embodiment of FIG. 5, however, rather thanemploying the switchable resistor 510, the DAC 700 instead employs asubcircuit 710 between the base resistor 709 and the plurality ofadditional resistors 712. As shown, the subcircuit 710 particularlyincludes a plurality of resistors 711 and a plurality of switches 713.Each of the resistors 711 is coupled in parallel with a respective oneof the switches 713, and the successive parallel combinations of theresistors and switches are coupled in series with one another between afirst node 715 of the subcircuit 710 and a second node 717 of thesubcircuit. The resistance of each of the resistors 711 can be anarbitrary number, and in some embodiments the resistances of thedifferent resistors can be of equal value or take on different values,although in the present embodiment the resistances are all equal (shownas 0.25 R). Further as shown, the plurality of additional resistors 712particularly includes two resistors, a first additional resistor 732 anda second additional resistor 734 (which in the present example are shownto have a resistance R). The base resistor 509 (also shown in thisexample to have a resistance 0.25 R) particularly is coupled between thefirst node 715 and the ground terminal 716, and the second node 717 iscoupled to the first additional resistor 732 of the plurality ofadditional resistors 712. Additionally, the first additional resistor732 is coupled between the second node 717 and the second additionalresistor 734, which in turn is coupled between the first additionalresistor 732 and the biasing current source 702.

Additionally, the switches 714 particularly include a first switch 724and a plurality of additional switches 726 that in the presentembodiment include first, second, third, and fourth additional switches728, 729, 730, and 731, respectively. The first switch 724 links thefirst node 715 with the non-inverting terminal 718, the first additionalswitch 728 links the second node 717 with the non-inverting terminal718, the second and third additional switches 729, 730 each link thenon-inverting terminal 718 with a node coupling the first and secondadditional resistors 732, 734, and the fourth switch 731 links thenon-inverting terminal with the node coupling the second additionalresistor 734 with the biasing current source 702. The presence of dashedlines 736 between the first and second additional resistors 732, 734 isintended to signify that any arbitrary number n of the additionalresistors 712 (and particularly any arbitrary number n>1) can be presentdepending upon the embodiment, and also to signify that correspondinglyany arbitrary number n>2 (or alternatively n>1) of the additionalswitches 726 can be present depending upon the embodiment.

Further in addition to the above aspects, FIG. 7 also shows controlcircuit components 748 of the DAC 700 that are employed to controloperation of the DAC, and particularly are employed to control theopening and closing, and the timing of such opening and closing, of theswitches 724, 713, and 726. More particularly as shown, the controlcircuit components 748 include first, second and third input ports 750,752, and 754, respectively, at which are provided a clock signal 756, azero-crossing signal 758, and a phase signal 760. The clock signal 756can (but need not) include or correspond to any of the clock signals308, 310, or 312 of FIG. 3. The zero-crossing signal 758 can (but neednot) include or correspond to the input signal 306 of FIG. 3. The phasesignal (or signals) 760 can be utilized to indicate the input phase ofthe input signal such as the input signal 306.

Additionally as shown, the control circuit components 748 includes aplurality of flip-flops (FFs) 762 that, in the present example,particularly include first, second, third, fourth, fifth, and sixthflip-flops 764, 765, 766, 767, 768, and 769, respectively. As indicatedby additional ones of the dashed lines 736, the number of the flip-flops762 that are present will correspond in part to the number of theswitches 714 and, in the present example, will exceed the number of theswitches 714 by one. As shown, the first input port 750 is tied to eachof flip-flops 762 such that the clock signal 756 is provided to each ofthe flip-flops. Further, the second input port 752 is coupled to thefirst flip-flop 764, which in turn is coupled by a first link 771 to thesecond flip-flop 765, which in turn is coupled by a second link 772 tothe third flip-flop 766. The third flip-flop 766 in turn is coupled by athird link 773 to the fourth flip-flop 767, which in turn is coupled bya fourth link 774 to the fifth flip-flop 768, which in turn is coupledby a fifth link 775 to the sixth flip-flop 769.

Additionally, the control circuit components 748 also include a firstdecoder 770. As shown, the third input port 754 is coupled to thedecoder 770 and, additionally, the first link 771 also links each of thefirst and second flip-flops 764 and 765 with the first decoder 770, suchthat the output signal of the first flip-flop 764 is provided to thatdecoder. Further as illustrated by control lines 780, the first decoder770 controls the open/closed status of each of switches 713.Additionally, the second link 772 further couples the second and thirdflip-flops 765, 766 with the first switch 724 such that the output ofthe second flip-flop 765 governs the open/closed status of that switch,and the third link 773 couples the third and fourth flip-flops 766, 767with the first additional switch 728 such that the output of the thirdflip-flop 766 governs the open/closed status of that switch. Also, thefourth link 774 couples the fourth and fifth flip-flops 767, 768 witheach of the switches 729 and 730 such that the output of the fourthflip-flop 767 governs the open/closed status of those switches. Further,the fifth link 775 couples the fifth and sixth flip-flops 768, 769 withthe switch 731 such that the output of the fifth flip-flop 768 governsthe open/closed status of that switch. Also, an additional link 776couples the sixth flip-flop 769 with the decoder 770 as well, such thatoperation of the decoder 770 also is based at least in part upon theoutput of that sixth flip-flop.

Based upon a comparison of FIG. 3 and FIG. 7, it should again berecognized that the circuit of FIG. 7 is capable of operating togenerate an output signal I_(out) that corresponds to any of the outputsignals 322, 332, and 342, and that this is achieved by appropriateactuation of the switches 713, 724, and 726 depending upon the phase ofthe clock signal 756. More particularly, based upon the phase of theclock signal 756, the decoder 770 causes the switches 713 to be openedor closed in an appropriate manner so as to increase or decrease thevoltages experienced at the various nodes between subcircuit 710 and thecurrent source 702. Such actuation of the switches 713—at a time whenthe DAC 700 also causes the first switch 724 to become opened instead ofclosed, further causes the first additional switch 728 to become closedinstead of opened, and further causes each of the additional switches729, 730, and 731 to remain opened—results in the application of avoltage to the non-inverting terminal 718 so as to produce a first stepin the output signal I_(out). The first step in the output signalI_(out) that is produced by such operation particularly is consistentwith having a virtual starting point that occurs at the time 320,regardless of the timing of the clock signal.

Additionally, to achieve subsequent steps in the output I_(out) that arerespectively consistent with the subsequent steps 356, 366, and 376 ofFIG. 3, the control circuit components 748 of the DAC 700 cause furtherchanges to the status of the switches 714. More particularly, to achievethe subsequent steps, the switch 728 is subsequently opened at the sametime one or both of the switches 729 and 730 are closed, and thenfurther the switches 729, 730 are again opened and the switch 731 isclosed. It should additionally be appreciated that, although notillustrated in FIG. 7, the DAC 700 in alternate embodiments can bemodified so that the output signal I_(out) will attain (or not surpass)a maximum value (or consistent end value) at a last step prior toreturning to an initial value. In view of the DAC 600 of FIG. 6, it willbe appreciated that such alternate embodiments can be achieved, forexample, by including an additional subcircuit with multiple resistorsand switches (identical or substantially similar to the subcircuit 710)coupled between the current source 702 and the second (or final)additional resistor 734 of the additional resistors 726. Desiredoperation involving such an additional subcircuit can be achieved, forexample, by appropriately controlling the actuation of the resistors andswitches of the additional subcircuit by way of an additional decoder,so that the actuation of the additional subcircuit is substantially theinverse of the actuation of the subcircuit 710.

Notwithstanding the description provided above, the present disclosureis intended to encompass numerous other embodiments and variations ofthe embodiments described or shown herein. For example, although thecontrol circuit components 648, 748 described in relation to FIGS. 6 and7 entail discrete components such as decoders and flip-flops, in otherembodiments one or more other types of components can be employedinstead of or in addition to such discrete components including, forexample, one or more microprocessors, microcomputers, programmable logicdevices (PLDs), and/or other control components. In general, the termcomponent as employed herein should be understood as encompassing one ormore devices, components, or subcomponents.

Further for example, at least some embodiments encompassed herein relateto a system for providing an output signal based at least in part uponan input signal and a clock signal in a manner in which jitter isavoided or diminished notwithstanding one or more phase changes of theclock signal. The system includes an output signal generating componentconfigured to perform a generating of the output signal, and a firstcomponent coupled at least indirectly to the output signal generatingcomponent, the first component having at least one first switch and afirst variable characteristic. The system also includes a plurality ofsecond components each having a respective additional switch and arespective fixed characteristic and coupled at least indirectly with thefirst component and the output signal generating component. In suchembodiment, a switching status of the at least one first switchdetermines a first time at which the first variable characteristicbegins to influence at least indirectly the generating of the outputsignal by the output signal generating component. Also, a first value ofthe first variable characteristic is set at least in part based upon theinput signal and the clock signal so that, when the first variablecharacteristic influences at least indirectly the generating of theoutput signal by the output signal generating component, the outputsignal attains at the first time a first level that is at leastindirectly dependent upon a phase of the clock signal relative to theinput signal. Further, a respective additional switching status of eachof the respective additional switches of each of the respective secondcomponents, respectively, determines a respective additional time atwhich the respective fixed characteristic of the respective secondcomponent begins to influence at least indirectly the generating of theoutput signal of the output signal generating component. Additionally,the additional switches are controlled so that the respective fixedcharacteristics of the respective second components successivelyinfluence at least indirectly the generating of the output signal by theoutput signal generating component at successive ones of the additionaltimes, respectively, so that the output signal attains respectivesequentially-larger levels at the respective additional times.

Also for example, at least some embodiments encompassed herein relate toa digital-to-analog converter (DAC) configured to provide an outputsignal based at least in part upon an input signal and a clock signal ina manner in which jitter is avoided or diminished notwithstanding one ormore phase changes of the clock signal. The DAC includes a transistordevice having first, second, and third terminals, the first terminalbeing an output terminal in relation to which is communicated the outputsignal. Additionally, the DAC also includes an operational amplifierhaving an inverting port, a non-inverting port, and an output port,where the output port is directly coupled to the second terminal of thetransistor device, and either the inverting port or the non-invertingport is directly coupled to the third terminal. Further, the DAC alsoincludes a first biasing component at least indirectly coupled to eitherthe inverting port or the non-inverting port, and including any of acurrent source, a voltage source, or a resistor. Additionally, the DACincludes a first component having at least one first switch and a firstvariable characteristic coupled directly with a first one of theinverting and non-inverting ports, and a plurality of second componentseach having a respective additional switch and a respective fixedcharacteristic, where each of the second components is coupled directlywith either the first component or a respective other one of the secondcomponents. In such embodiment, respective actuations of the at leastone first switch and the additional switches occur at or substantiallyproximate to respective successive times at which respective levelchanges in the clock signal occur, respectively, such that the outputsignal takes on respective increased levels at or substantiallyproximate to the respective successive times. Further, the actuation ofthe at least one first switch is configured so that, or another actionis taken in relation to the first component so that, a first value ofthe first variable characteristic is at least indirectly applied to orexperienced by the first one of the inverting and non-inverting ports ator proximate to a first one of the successive times. Additionally, dueto the first value of the first variable characteristic and eachrespective fixed characteristic, an effective slope associated with theoutput signal passes through a starting level at or substantiallyproximate to a zero-crossing time of the input signal.

Also for example, at least some embodiments encompassed herein relate toa method of providing an output signal based at least in part upon aninput signal and a clock signal in a manner in which jitter is avoidedor diminished notwithstanding one or more phase changes of the clocksignal relative to the input signal. The method includes detecting botha first value of the input signal at a first time at which the clocksignal experiences a first level change and also a second value of theinput signal at a second time at which the clock signal experiences asecond level change, the first time preceding a zero-crossing time ofthe input signal and the second time occurring after the zero-crossingtime. The method also includes determining a first change value at leastindirectly based upon the first and second values and based upon astandard step height value, and switching at least one switch so as tocause the output signal to change from a starting level to a first steplevel based at least in part upon the first change value at orsubstantially proximate to the second time. Additionally, the methodfurther includes switching first and second additional switchesrespectively at or proximate to third and fourth times, respectively, atwhich the clock signal experiences third and fourth level changes,respectively, so as to cause the output signal to change from the firststep level to a second step level and then to a third step level,respectively, at or proximate to the third and fourth times,respectively. Further, in such embodiment, the starting level, firststep level, second step level, and third step level of the output signalare such that an effective slope associated with the output signalpasses through the starting level at or substantially proximate to thezero-crossing time, whereby, notwithstanding the one or more phasechanges in the clock signal, the output signal substantially or entirelyretains a consistent phase relative to the input signal over a timeperiod corresponding to a plurality of periods of the clock signal.

In view of the above discussion, it will be appreciated that embodimentsof DACs and systems and methods employing such DACs such as thosedescribed above or otherwise encompassed herein can provide any of avariety of advantages. Among other things, at least some such circuits,systems and methods can allow for a new manner of slope generation thatcan substantially reduce or eliminate the jitter caused by quantizationin the time domain. Such DACs or associated systems or methods allow forthe use of a slow clock while maintaining a low jitter on the outputsignal. Additionally, at least some DACs and systems employing suchDACs, such as speed sensor systems, encompassed herein, can be employedin a variety of applications including, for example, automotiveapplications. Indeed, DACs and systems employing such DACs, such asspeed sensor systems, as encompassed herein, can be employed in avariety of products, including products having high-level or specificrequirements relating to the jitter of an output signal.

While the principles of the invention have been described above inconnection with specific apparatus, it is to be clearly understood thatthis description is made only by way of example and not as a limitationon the scope of the invention. It is specifically intended that thepresent invention not be limited to the embodiments and illustrationscontained herein, but include modified forms of those embodimentsincluding portions of the embodiments and combinations of elements ofdifferent embodiments as come within the scope of the following claims.

What is claimed is:
 1. A system for providing an output signal based atleast in part upon an input signal and a clock signal in a manner inwhich jitter is avoided or diminished notwithstanding one or more phasechanges of the clock signal, the system comprising: an output signalgenerating component configured to perform a generating of the outputsignal; a first component coupled at least indirectly to the outputsignal generating component, the first component having at least onefirst switch and a first variable characteristic; a plurality of secondcomponents each having a respective additional switch and a respectivefixed characteristic and coupled at least indirectly with the firstcomponent and the output signal generating component; wherein aswitching status of the at least one first switch determines a firsttime at which the first variable characteristic begins to influence atleast indirectly the generating of the output signal by the outputsignal generating component, wherein a first value of the first variablecharacteristic is set at least in part based upon the input signal andthe clock signal so that, when the first variable characteristicinfluences at least indirectly the generating of the output signal bythe output signal generating component, the output signal attains at thefirst time a first level that is at least indirectly dependent upon aphase of the clock signal relative to the input signal, wherein arespective additional switching status of each of the respectiveadditional switches of each of the respective second components,respectively, determines a respective additional time at which therespective fixed characteristic of the respective second componentbegins to influence at least indirectly the generating of the outputsignal of the output signal generating component, and wherein theadditional switches are controlled so that the respective fixedcharacteristics of the respective second components successivelyinfluence at least indirectly the generating of the output signal by theoutput signal generating component at successive ones of the additionaltimes, respectively, so that the output signal attains respectivesequentially-larger levels at the respective additional times.
 2. Thesystem of claim 1, wherein the output signal generating componentincludes a transistor device, and wherein the first time and eachadditional time coincides with a respective level change of the clocksignal.
 3. The system of claim 2, wherein the transistor device includesa metal oxide semiconductor field effect transistor (MOSFET).
 4. Thesystem of claim 3, further comprising: an operational amplifier havingan output terminal coupled to a gate of the MOSFET; and a biasingcomponent coupled at least indirectly between a ground terminal andeither an inverting or non-inverting terminal of the operationalamplifier, the biasing component including one or more of a resistor, acurrent source, and a voltage source.
 5. The system of claim 2, furthercomprising an operational amplifier, wherein the transistor deviceincludes a first terminal and the operational amplifier includes a firstport, and wherein the first terminal is directly coupled with the firstport.
 6. The system of claim 5, wherein the operational amplifierincludes at least one second port, wherein the at least one second portis directly coupled with the first component and either directly coupledwith, or indirectly coupled by way of the first component with, theplurality of second components.
 7. The system of claim 1, wherein thefirst component includes either a first switchable current source or afirst variable resistor that is connected in series with the at leastone first switch.
 8. The system of claim 7, wherein the first componentincludes the first switchable current source and the first value of thefirst variable characteristic is determined by a setting of the firstswitchable current source.
 9. The system of claim 7, wherein the firstcomponent includes the first variable resistor and the first value ofthe first variable characteristic is determined by a resistance settingof the first variable resistor.
 10. The system of claim 1, wherein thefirst component includes a plurality of resistors and the at least onefirst switch of the first component includes a plurality of firstswitches, wherein each of the resistors of the plurality of resistors iscoupled either in series or in parallel with a respective one of thefirst switches of the plurality of first switches.
 11. The system ofclaim 10, wherein the switching status of the at least one first switchincludes a plurality of subsidiary switching statuses respectivelyassociated with respective ones of the first switches, respectively, andwherein the first value of the first variable characteristic isdetermined by a setting of subsidiary switching statuses.
 12. The systemof claim 11, further comprising a control component that is coupled atleast indirectly with the at least one first switch and determines thesubsidiary switching statuses of the first switches.
 13. The system ofclaim 12, wherein the control component includes a decoder or amicroprocessor.
 14. The system of claim 13, wherein the controlcomponent additionally includes one or more flip-flops that are coupledat least indirectly with the additional switches and that determine theadditional switching statuses of the additional switches of the secondcomponents.
 15. The system of claim 1, further comprising: a furthercomponent coupled at least indirectly to the output signal generatingcomponent, the first component having at least one second switch and asecond variable characteristic, wherein a further switching status ofthe at least one second switch determines a further time at which thesecond variable characteristic begins to influence at least indirectlythe generating of the output signal by the output signal generatingcomponent.
 16. The system of claim 15, wherein the second variablecharacteristic is substantially an inverse of the first variablecharacteristic, wherein a switching status of the at least one firstswitch is determined by a first decoder of a control component of thesystem, and the further switching status of the at least one secondswitch is determined by a second decoder of the control component. 17.The system of claim 1, wherein the system operates as a speed sensingsystem and additionally includes one or more sensors that provide one ormore sensor signals, and wherein the input signal is based at leastindirectly upon the one or more sensor signals.
 18. A digital-to-analogconverter (DAC) configured to provide an output signal based at least inpart upon an input signal and a clock signal in a manner in which jitteris avoided or diminished notwithstanding one or more phase changes ofthe clock signal, the DAC comprising: a transistor device having first,second, and third terminals, the first terminal being an output terminalin relation to which is communicated the output signal; an operationalamplifier having an inverting port, a non-inverting port, and an outputport, wherein the output port is directly coupled to the second terminalof the transistor device, and either the inverting port or thenon-inverting port is directly coupled to the third terminal; a firstbiasing component at least indirectly coupled to either the invertingport or the non-inverting port, and including any of a current source, avoltage source, or a resistor; a first component having at least onefirst switch and a first variable characteristic coupled directly with afirst one of the inverting and non-inverting ports; a plurality ofsecond components each having a respective additional switch and arespective fixed characteristic, wherein each of the second componentsis coupled directly with either the first component or a respectiveother one of the second components, wherein respective actuations of theat least one first switch and the additional switches occur at orsubstantially proximate to respective successive times at whichrespective level changes in the clock signal occur, respectively, suchthat the output signal takes on respective increased levels at orsubstantially proximate to the respective successive times, wherein theactuation of the at least one first switch is configured so that, oranother action is taken in relation to the first component so that, afirst value of the first variable characteristic is at least indirectlyapplied to or experienced by the first one of the inverting andnon-inverting ports at or proximate to a first one of the successivetimes, and wherein due to the first value of the first variablecharacteristic and each respective fixed characteristic, an effectiveslope associated with the output signal passes through a starting levelat or substantially proximate to a zero-crossing time of the inputsignal.
 19. The DAC of claim 18, further comprising at least one controlcomponent, and wherein the DAC either has a current configuration inwhich the first component is directly coupled with the inverting port ora voltage configuration in which the first component is directly coupledwith the non-inverting port.
 20. A method of providing an output signalbased at least in part upon an input signal and a clock signal in amanner in which jitter is avoided or diminished notwithstanding one ormore phase changes of the clock signal relative to the input signal, themethod comprising: detecting both a first value of the input signal at afirst time at which the clock signal experiences a first level changeand also a second value of the input signal at a second time at whichthe clock signal experiences a second level change, the first timepreceding a zero-crossing time of the input signal and the second timeoccurring after the zero-crossing time; determining a first change valueat least indirectly based upon the first and second values and basedupon a standard step height value; switching at least one switch so asto cause the output signal to change from a starting level to a firststep level based at least in part upon the first change value at orsubstantially proximate to the second time; switching first and secondadditional switches respectively at or proximate to third and fourthtimes, respectively, at which the clock signal experiences third andfourth level changes, respectively, so as to cause the output signal tochange from the first step level to a second step level and then to athird step level, respectively, at or proximate to the third and fourthtimes, respectively, wherein the starting level, first step level,second step level, and third step level of the output signal are suchthat an effective slope associated with the output signal passes throughthe starting level at or substantially proximate to the zero-crossingtime, whereby, notwithstanding the one or more phase changes in theclock signal, the output signal substantially or entirely retains aconsistent phase relative to the input signal over a time periodcorresponding to a plurality of periods of the clock signal.